The present invention relates to a logical comparison circuit which permits a logical comparison between the output (a signal to be compared) from an IC element under test and an expected value signal both in an interleaved form and the logical comparison at two phase-shifted timings set in one operation period (or test period).
FIG. 1 shows a conventional logical comparison circuit, the operation of which will be described first with reference to a timing chart depicted in FIG. 2. A first comparison clock (strobe) C1 of the same period as a test cycle period Ts is provided from a clock input terminal 11 to a 1-to-4 frequency dividing counter 12, which provides at its four output terminals frequency-divided outputs C.sub.1, C.sub.2, C.sub.3, C.sub.4 (only C.sub.1 and C.sub.2 shown in FIG. 2) of a period 4Ts which are phased the period Ts apart in a sequential, repeating cyclic order. The four frequency-divided output are supplied to gates 13.sub.1 to 13.sub.4 and the first comparison clock C1 at the terminal 11 is applied to the gates 13.sub.1 to 13.sub.4 in common thereto. As the result of this, clocks of the period 4Ts, cyclically displaced the period Ts apart in phase, are obtained at outputs of the gates 13.sub.1 to 13.sub.4. By these outputs comparison signals A, that is, outputs A1, A2, A3, . . . from an IC element under test (not shown), are cyclically latched in latch circuits 15.sub.1 to 15.sub.4, from which signals B.sub.1, B.sub.2, B.sub.3, B.sub.4 (only B.sub.1 and B.sub.2 shown in FIG. 2) are output. Consequently, the output signal B.sub.1 of the latch 15.sub.1, for example, is composed of demultiplexed comparison data A1, A5, A9, . . . and the time length of each data has been expanded four times longer than the time length of data of the signal A.
A first system clock S1 from a clock input terminal 16, which has the same period as that of the first comparison clock C1, is frequency divided by a 1-to-4 frequency dividing counter 17 similar to the counter 12. The frequency-divided outputs from the 1-to-4 frequency dividing counter 17 are supplied to gates 18.sub.1 to 18.sub.4, respectively, and the first system clock S1 is applied to terminals of the gates 18.sub.1 to 18.sub.4 from the terminal 16. An expected value signal E from a terminal 19 is latched in latch circuits 21.sub.1 to 21.sub.4 by the outputs of the gates 18.sub.1 to 18.sub.4. Hence, the latches 21.sub.1 to 21.sub.4 output signals D.sub.1 (E.sub.1, E.sub.5, E.sub.9, . . . ) to D.sub.4 (E.sub.4, E.sub.8, E.sub.12, . . . ) four times longer than the expected value signal E as is the case with the signal A.
The corresponding ones of the outputs B.sub.1 to B.sub.4 from the latch circuits 15.sub.1 to 15.sub.4 and the outputs D.sub.1 to D.sub.4 from the latch circuits 21.sub.1 to 21.sub.4 are compared in comparators 22.sub.1 to 22.sub.4 each formed by an exclusive OR circuit, from which comparison result signals F.sub.1 to F.sub.4 (only F.sub.1 and F.sub.2 shown in FIG. 2) are output. A second system clock S2 from a clock input terminal 23 is frequency divided by a 1-to-4 frequency dividing counter 24 similar to those mentioned above, and corresponding ones of four frequency-divided outputs G.sub.1 to G.sub.4 from the 1-to-4 frequency dividing counter 24 (similar to the outputs C.sub.1 to C.sub.4 of the counter 12) and the outputs F.sub.1 to F.sub.4 from the comparators 22.sub.1 to 22.sub.4 are respectively applied to AND circuits 25.sub.1 to 25.sub.4. Thus the AND circuits 25.sub.1 to 25.sub.4 are enabled for the time TS in a sequential, repeating cyclic order, permitting the passage therethrough of the corresponding signals F.sub.1 to F.sub.4 accordingly. The outputs H.sub.1 to H.sub.4 from the AND circuits 25.sub.1 to 25.sub.4 applied to an OR circuit 26, wherein they are subjected to time division multiplexing, thereafter being provided as a decision result J to an output terminal 27 at the same data rate as that of the comparison signal A.
As described above, the signals A and E to be compared are each demultiplexed to plural pieces of data of expanded period and the corresponding ones of them are compared in parallel, after which the results of comparison are time-division-multiplexed for return to the same data rate as that of the input comparison signal A. In this way, the logical comparison of high-speed signals can accurately be made using circuits of law operating speed and the timing for comparison can be set at an arbitrary point of time within a period T1 longer than that Ts as shown in Row C1 of FIG. 2.
Incidentally, there is a case where a test is made to determine if the changing point of data of the comparison signal A, which is applied to the terminal 14, is within a predetermined limit. In such a test two comparison timings of two out-of-phase first and second comparison clocks C1 and C2, which define the limit, are set in the operation period Ts as shown in FIG. 3 and the comparison test is made at the timing of each comparison clock.
To this end, the prior art combines the circuit of FIG. 1 with a circuit of FIG. 4 which is composed of circuits similar to the counter 12, the gates 13.sub.1 to 13.sub.4, the latches 15.sub.1 to 15.sub.4, comparators 22.sub.1 to 22.sub.4, the gates 25.sub.1 to 25.sub.4 and the OR circuit 26 in FIG. 1. The second comparison clock C2 from a clock input terminal 28 is frequency divided by a 1-to-4 frequency dividing counter 29 and its four frequency-divided outputs are applied to gates 31.sub.1 to 31.sub.4, respectively. The second comparison clock C2 applied to the gates 31.sub.1 to 31.sub.4 in common thereto from the terminal 28 and the outputs of the gates 31.sub.1 to 31.sub.4 are provided to latch circuits 32.sub.1 to 32.sub.4 to latch therein the comparison signal A from the terminal 14 in FIG. 1. The outputs of the latch circuits 32.sub.1 to 32.sub.4 and the outputs of the latch circuits 21.sub.1 to 21.sub.4 in FIG. 1 are compared in comparators 33.sub.1 to 33.sub.4, respectively, and the corresponding ones of the outputs from the comparators 33.sub.1 to 33.sub.4 and the four outputs from the counter 24 in FIG. 1 are supplied to AND circuits 34.sub.1 to 34.sub.4, respectively. The outputs of the AND circuits 34.sub.1 to 34.sub.1 are provided to an OR circuit 35, from which the result of decision about the comparison at the timing of the second comparison clock C2 is provided to an output terminal 36.
Thus it is necessary in the prior art, for simultaneous setting of two comparison timings in one operation period Ts, to use a pair of circuits which are exactly the same as that including the 1-to-4 frequency dividing counter 12, the gates 13.sub.1 to 13.sub.4, the latch circuits 15.sub.1 to 15.sub.4, the comparators 22.sub.1 to 22.sub.4 and the AND circuits 25.sub.1 to 25.sub.4 in FIG. 1. Normally the comparison timing in one operation period is at one point of time and, on rare occasions, at two points. Hence the prior art involves an appreciable amount of extra hardware for setting two comparison timings but it is not frequently used and is left out of operation at almost all times.